`timescale 1ns/1ps

module tb_main;

// design_main Parameters
`define mode0

`ifdef mode0
    parameter IMEM_MEMFILE = "../../soft/test1.txt";
    parameter DMEM_MEMFILE = "../../soft/test1_DMEM.txt";
`endif

`ifdef mode1
    parameter IMEM_MEMFILE = "../../soft/test2.txt";
    parameter DMEM_MEMFILE = "../../soft/test2_DMEM.txt";
`endif


// design_main Inputs
reg   clk;
reg   rst_n;

// design_main Outputs


design_main #(
    .IMEM_InitEn  ( 1            ),      
    .IMEM_MEMFILE ( IMEM_MEMFILE ),      
    .DMEM_InitEn  ( 1            ),      
    .DMEM_MEMFILE ( DMEM_MEMFILE ))      
 u_design_main (
    .clk                     ( clk     ),
    .rst_n                   ( rst_n   ) 
);


always #10 clk = ~ clk;

initial begin
    clk = 0;
    rst_n = 0;
#20
    rst_n = 1;
end


endmodule
